TIMER B
8.4 Event counter mode
8.4.3 Operation in event counter mode
✕ When the count start bit is set to “1,” the counter starts counting of the count source.
✕ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
✕ The timer Bi interrupt request bit is set to “1” at the counter underflow in ✕.
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 8.4.4 shows an example of operation in the event counter mode.
FFFF16
Starts counting.
Stops counting.
n
Restarts counting .
000016
Time
Cleared to “0” by
software.
Set to “1” by software.
Set to “1” by software.
Count start bit
Timer Bi interrupt
request bit
n : Reload ragister’s contents
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
Fig. 8.4.4 Example of operation in event counter mode
7906 Group User’s Manual Rev.2.0
8-17
RENESAS [ RENESAS TECHNOLOGY CORP ]
