TIMER B
8.4 Event counter mode
(b8)
b0 b7
(b15)
b7
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
b0
Function
Any value in the range from “000016” to “FFFF16” can be set.
Bit
At reset R/W
15 to 0
Undefined RW
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
b7 b6 b5 b4 b3 b2 b1 b0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
X X X
0 1
X
Bit
0
Bit name
Function
At reset R/W
b1 b0
Operating mode select bits
0
0
0
RW
RW
RW
0 1 : Event counter mode
1
b3 b2
Count polarity select bits
2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Count at both falling and rising edges of external
signal
3
0
RW
1 1 : Do not select.
(Note)
This bit is invalid in event counter mode.
4
5
0
—
This bit is invalid in event counter mode; its value is undefined at reading.
RO
Undefined
These bits are invalid in event counter mode.
6
7
RW
RW
0
0
X : It may be either “0” or “1.”
Note: When the timer B2 clock source select bit (bit 6 at address 6316) = “1,” be sure to fix these bits to “012” (count at the rising
edge of the external signal).
Fig. 8.4.1 Structures of timer Bi register and timer Bi mode register in event counter mode
7906 Group User’s Manual Rev.2.0
8-14
RENESAS [ RENESAS TECHNOLOGY CORP ]
