TIMER A
[Precautions for pulse width modulation (PWM) mode]
[Precautions for pulse width modulation (PWM) mode]
1. Each of timers A3, A5 to A8 is not equipped with the pulse width modulation (PWM) mode.
2. If the count start bit is cleared to “0” during PWM pulse output, the counter stops counting. If the TAjOUT
pin outputs “H” level at that time, the output level will become “L” and the timer Aj interrupt request bit
will be set to “1.” When the TAjOUT pin outputs “L” level at that time, the output level will not change and
no timer Aj interrupt request will occur.
3. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request
bit is set to “1.”
➀When the PWM mode is selected after reset
➀When the operating mode is switched from the timer mode to the PWM mode
➀When the operating mode is switched from the event counter mode to the PWM mode
Accordingly, when using a timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt
request bit to “0” after the above setting.
7906 Group User’s Manual Rev.2.0
7-47