INTERRUPTS
6.6 Interrupt priority level detection time
6.6 Interrupt priority level detection time
When the interrupt priority level detection time has passed after sampling starts, an interrupt request is
accepted. The interrupt priority level detection time can be selected by software. (See Figure 6.6.1.) Usually,
select “2 cycles of fsys” as the interrupt priority level detection time.
Figure 6.6.2 shows the interrupt priority level detection time.
b7 b6 b5 b4 b3 b2 b1 b0
Processor mode register 0 (Address 5E16)
0
0
X X
0
Bit
0
Bit name
Function
At reset
R/W
RW
b1 b0
Processor mode bits
0
0 0 : Single-chip mode
0 1 : Do not select.
1 0 : Do not select.
1 1 : Do not select.
0
1
RW
2
3
4
Any of these bits may be either “0” or “1.”
0
1
0
RW
RW
RW
b5 b4
Interrupt priority detection time
select bits
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
5
RW
WO
RW
0
0
0
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
Software reset bit
6
7
Fix this bit to “0.”
X : It may be either “0” or “1.”
Fig. 6.6.1 Structure of processor mode register 0
f
sys
Op-code fetch cycle
Sampling pulse
(Note)
(a) 7 cycles of fsys
(b) 4 cycles of fsys
Interrupt priority level
detection time
(c) 2 cycles of fsys
Note: The pulse resides when “2 cycles of fsys” is selected.
Fig. 6.6.2 Interrupt priority level detection time
7905 Group User’s Manual Rev.1.0
6-12
RENESAS [ RENESAS TECHNOLOGY CORP ]
