A-D CONVERTER
12.7 One-shot mode
Continued from preceding Figure 12.7.1.
Selection of comparator function
b7
b0
b7
b0
Comparator function select register 1
Comparator function select register 0
0
0 0 0
(Address DD16
)
(Address DC16
)
AN
AN
AN10
AN11
8
9
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
0 : Comparator function is not selected
1 : Comparator function is selected.
0 : Comparator function is not selected
1 : Comparator function is selected.
When comparator function is not selected
When comparator function is selected
A-D register i
A-D register 0 (Addresses 2116, 2016
A-D register 1 (Addresses 2316, 2216
A-D register 2 (Addresses 2516, 2416
A-D register 3 (Addresses 2716, 2616
A-D register 4 (Addresses 2916, 2816
)
)
)
)
)
(b 8)
b0
(b15)
b7
b7
b0
A-D register 5 (Addresses 2B16, 2A16
)
A-D register 6 (Addresses 2D16, 2C16
)
A-D register 7 (Addresses 2F16, 2E16
A-D register 8 (Addresses E116, E016
A-D register 9 (Addresses E316, E216
A-D register 10 (Addresses E516, E416
A-D register 11 (Addresses E716, E616
)
)
)
)
)
A value (comparison value) in the range
from 0016 through FF16 is set.
Interrupt priority level
b7
b0
A-D conversion interrupt control register
(Address 7016
0
)
Interrupt priority level select bits
Set the level to one of 1 through 7 when using this interrupt
Set the level to 0 when disabling interrupts.
No interrupt requested
Port P7, P8 direction register
b7
b0
b7
b0
Port P8 direction register
(Address 1416
Port P7 direction register
)
(Address 1116
)
AN
AN
AN10
AN11
8
9
AN
0
1
2
3
4
5
6
7
Clear the bits, corresponding to the
selected analog input pins, to “0.”
AN
AN
AN
AN
AN
AN
AN
Clear the bits, corresponding to the
selected analog input pins, to “0.”
Setting of A-D conversion start bit to “1.”
b7
b0
A-D control register 0
(Address 1E16
1
)
A-D conversion start bit
Trigger generated
Operation starts.
Note: Writing to the following must be performed while the A-D converter
halts (in other words, before a trigger is generated); this must be done
independent of the operation mode of the A-D converter.
• Each bit of the A-D control register 0, except writing of “0” to bit 6
• Each bit of the A-D control register 1
• Each bit of the A-D control register 2
• A-D register i (when the comparator function is selected)
• Comparator function select register 0
• Comparator function select register 1
Especially, when the VREF connection select bit is cleared from “1” to “0,”
an interval of 1 µs or more must be elapsed before occurrence of a trigger.
Fig. 12.7.2 Initial setting example for related registers in one-shot mode (2)
7905 Group User’s Manual Rev.1.0
12-24
RENESAS [ RENESAS TECHNOLOGY CORP ]
