CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit (BIU)
2.2 Bus interface unit (BIU)
The bus interface unit (hereafter called “BIU”) performs the following two operations:
q
Instruction prefetch
q
Data transfer (read and write)
Figure 2.2.1 shows the bus and BIU.
BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU
registers.
M37905
Internal buses
CPU bus
Central
processing
unit
(CPU)
Internal code bus (CB
0
to CB
31
)
Bus
interface
unit
(BIU)
Internal data bus (DB
0
to DB
15
)
Internal address bus (AD
0
to AD
23
)
Internal control signal
Internal
memory
Internal
peripheral
devices
(SFR)
SFR : Special Function Register
❈
The CPU bus and internal bus are independent of one another.
Fig. 2.2.1 Bus and BIU
Table 2.2.1 Functions of BIU registers
Name
Functions
Program
Indicates a storage address of the
address
instruction to be fetched into an
register
instruction queue buffer, next.
Instruction
Temporarily stores an instruction
queue buffer which has been fetched.
Data address Indicates an address from which data
register
will be read or to which data will be
written, next.
Data buffer
Temporarily stores data which has
been read from memory•I/O device
by BIU or which will be written to
memory•I/O device by the CPU.
b23
b0
PA
b7
b0
Program address register
Q
0
Instruction queue buffer
Q
9
b23
b0
DA
b31
b0
Data address register
DQ
Data buffer
Fig. 2.2.2 BIU registers’ structure
In the M37905, the internal buses are used when the CPU accesses the internal area (the internal memory
and SFR).
2-10
7905 Group User’s Manual Rev.1.0
RENESAS [ RENESAS TECHNOLOGY CORP ]
