SERIAL I/O
11.2 Block description
11.2 Block description
Figure 11.2.1 shows the block diagram of serial I/O. Registers relevant to serial I/O are described below.
Data bus (odd)
Data bus (even)
Bit converter
D8
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
UARTi receive
buffer register
RxD
i
UARTi receive register
UART
1/16
1/16
1/2
BRG count source
select bits
Transfer clock
Transfer clock
Receive
control circuit
Clock
synchronous
f
2
BRGi
f
16
64
UART
f
1 / (n+1)
Transmit control
circuit
f
512
Clock
synchronous
Clock synchronous
(internal clock selected)
UARTi transmit register
TxDi
UARTi transmit
buffer register
Clock synchronous
(internal clock selected)
Clock synchronous
(external clock selected)
D8
D7 D6 D5 D4 D3 D2 D1 D0
Bit converter
CLKi
CTS
CTS
i
/CLK
i
Data bus (odd)
Data bus (even)
CTSi
i/RTS
i
n: Values set in UARTi baud rate register (BRGi)
Fig. 11.2.1 Block diagram of serial I/O
7905 Group User’s Manual Rev.1.0
11-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
