Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
Table 1.2 Functions and Specifications for M16C/6N Group (128-pin Version: M16C/6NM)
Item
CPU
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
Address space
Memory capacity
Ports
Multifunction timers
Specification
Normal-ver.
91 instructions
T/V-ver.
1. Overview
Peripheral
Function
Serial interfaces
A/D converter
D/A converter
DMAC
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
Clock generation circuits
Electrical
Characteristics
Oscillation-stopped detector
Supply voltage
Consumption Mask ROM
current
Flash memory
Mask ROM
Flash memory
Flash Memory Programming and erasure voltage
Version
Programming and erasure endurance
I/O
I/O withstand voltage
Characteristics Output current
Operating Ambient Temperature
Device Configuration
Package
NOTES:
1. I
2
C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, Single-chip mode
and microprocessor modes
1 Mbyte
Refer to
Table 1.3 Product Information
Input/Output: 113 pins, Input: 1 pin
Timer A: 16 bits
✕
5 channels
Timer B: 16 bits
✕
6 channels
Three-phase motor control circuit
3 channels
Clock synchronous, UART, I
2
C-bus
(1)
, IEBus
(2)
4 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits
✕
2 channels
2 channels
CRC-CCITT
2 channels with 2.0B specification
15 bits
✕
1 channel (with prescaler)
Internal: 34 sources, External: 12 sources
Software: 4 sources, Priority levels: 7 levels
4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Main clock oscillation stop and re-oscillation detection function
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
21 mA (f(BCLK) = 24 MHz,
-
PLL operation, no division)
23 mA (f(BCLK) = 24 MHz,
21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
PLL operation, no division)
3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
0.8 µA (Stop mode, Topr = 25°C)
3.0 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
100 times
5.0 V
5 mA
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
CMOS high-performance silicon gate
128-pin molded-plastic LQFP
Rev.2.10 Aug 25, 2006
REJ03B0058-02100
page 3 of 81
RENESAS [ RENESAS TECHNOLOGY CORP ]
