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16C6KA 参数 Datasheet PDF下载

16C6KA图片预览
型号: 16C6KA
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机说明 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description]
分类和应用: 计算机
文件页数/大小: 268 页 / 1996 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M16C/6KA Group  
Description  
The differences in M16C/6K (144-pin) group  
Type name  
M306K9FCLRP  
(In mass production)  
M306K7F8LRP(In mass production)  
M306KAFCLRP(Under development)  
144-pin  
Pin numbers  
RAM  
144-pin  
144-pin  
3K bytes  
5K bytes  
5K bytes  
NEW DINOR  
Flash memory 68K bytes  
NEW DINOR  
Flash memory 128K bytes  
NEW DINOR  
Flash memory 128K bytes  
ROM  
User ROM area  
Address 0EF00016 - 0FFFFF16  
Boot ROM area  
User ROM area  
Address 0E000016 - 0FFFFF16  
Boot ROM area  
User ROM area  
Address 0E000016 - 0FFFFF16  
Boot ROM area  
Built-in ROM area  
Address 0FF00016 - 0FFFFF16  
Address 0FF00016 - 0FFFFF16  
Address 0FF00016 - 0FFFFF16  
Flash memory recognition register  
Flash memory recognition register  
Flash memory recognition register  
After reset XXXXXX112  
Address 03B416  
Address 03B716  
After reset 00000000  
2
After reset XXXXXX10  
2
Flash memory control register  
Flash memory control register  
Flash memory control register  
After reset XX000001  
2
After reset 00000001  
2
After reset 00000001  
2
The power supply  
for program/erase  
Vcc 3.0 - 3.6V  
FVCC 3.0 - 3.6V  
Vcc 3.0 - 3.6V  
Vcc 3.0 - 3.6V  
The input pin of power supply  
for program/erase  
Not exist  
Not exist  
8-bit X 6  
FVCC pin  
PWM output circuit  
14-bit X 4  
8-bit X 6  
3 channels (I2C bus interface pin of Channel  
1 and 2 can changed.)  
2
I C bus interface  
2 channels  
3 channels  
8 inputs shared with 1 interrupt  
request X 1  
Key input interrupt  
8 inputs shared with 1 interrupt  
request X 1  
8 inputs shared with 1 interrupt  
request X 1  
8 inputs (with event latch) shared  
with 1 interrupt request X 1  
Detected only in the falling edge  
Can not be selected with 1 bit unit  
8 inputs (with event latch) shared  
with 1 interrupt request X 1  
Detected in either of the edges by  
the edge selection  
8 inputs (with event latch) shared  
with 1 interrupt request X 1  
Detected in either of the edges by  
the edge selection  
Can be selected with 1 bit unit  
Can be selected with 1 bit unit  
DMAC  
Exist (2 channels)  
Exist (2 channels)  
Not exist  
D/A converter  
Comparator Circuit  
Interrupts  
Exist (8-bit X 2 channels)  
Exist (8 channels)  
31 vector  
Exist (8-bit X 2 channels)  
Exist (8 channels)  
31 vector  
Not exist  
Not exist  
45 vector (add OBE int.)  
Serial I/O  
• UART or clock  
synchronous X 3  
• clock  
• UART or clock  
synchronous X 3  
• clock  
• UART or clock  
synchronous X 1  
• clock  
synchronous X 2  
synchronous X 2  
synchronous X 2  
Clock generation  
circuits  
2 circuits  
2 circuits  
1 circuit  
Rev.1.00 Jul 16, 2004 page 3 of 266  
REJ03B0100-0100Z