M16C/26 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
(Note 2)
PM0
PM1
CM0
CM1
0016
00001000
01001000
00100000
2
2
2
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register
(Note 3)
CM2
0X000000
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
XX16
00XXXXXX
0016
0016
X016
2(Note 4)
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1
Voltage detection register 2
(Note 5)
(Note 5)
VCR1
VCR2
00001000
0016
2
Processor mode register 2
Voltage down detection interrupt register
DMA0 source pointer
PM2
D4INT
SAR0
XXX00000
0016
XX16
XX16
XX16
2
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
XX16
XX16
XX16
TCR0
XX16
XX16
DM0CON
SAR1
00000X002
XX16
XX16
XX16
DAR1
XX16
XX16
XX16
TCR1
XX16
XX16
DM1CON
00000X002
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 4: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input
voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection
circuit enable).
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 12 of 37
REJ09B0176-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
