RTL8208B-LF/RTL8208BF-LF
Datasheet
9.5.6. SS-SMII Transmit Timing
Table 46. SS-SMII Transmit Timing
Symbol
Description
Minimum
Typical
Maximum
Units
T_ipsu_txd_s3mii
TXD/TX_SYNC setup time to
TX_CLK.
1.5
-
-
ns
T_iphd_txd_s3mii
TXD/TX_SYNC hold time from
TX_CLK.
1
-
-
ns
T_ipsu_txd_s3mii
T_iphd_txd_s3mii
TX_CLK
TXD
Valid Data
Figure 28. SS-SMII Transmit Timing
9.6. Power Start Up & Internal Reset Sequence
Figure 29. Power Start Up & Internal Reset Sequence
• tpou33: min. 1ms and max. 5ms, 3.3V power on to stable duration requirement.
• tpou18: min. 600µs and max. 2ms, 1.8V power on to stable duration requirement.
• tsr: min. 10ms after 1.8V Power Stable, stable supply voltage to reset high duration.
• trw: max. 50ms, Reset_wait (Start normal PHY after reset deassertion).
Single-Chip Octal 10/100-TX/FX PHY Transceiver
56
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
