RTL8208B-LF/RTL8208BF-LF
Datasheet
Asymmetric Pause – Setting this bit indicates the availability of Asymmetric Flow Control capabilities
when full duplex operation is in use. This bit is used by one MAC to communicate Asymmetric Pause
Capability to its Link Partner and has no effect on PHY operation.
Pause –Setting this bit indicates the availability of Flow Control capabilities when full duplex operation
is in use. This bit is used by one MAC to communicate Pause Capability to its Link Partner and has no
effect on PHY operation.
100Base-T4 – Because the RTL8208B(F)-LF does not support the T4 function, any reads to this bit will
return a ‘0’.
100Base-TX-FD – This bit advertises that the RTL8208B(F)-LF can operate in 100Base-TX full duplex
mode. Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip restores the
default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return
the last written value, or the default value if no write has been completed since the last reset.
100Base-TX – This bit advertises that the RTL8208B(F)-LF can operate in 100Base-TX half duplex
mode. Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the
default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return
the last written value, or the default value if no write has been completed since the last reset.
10Base-T-FD – This bit advertises that the RTL8208B(F)-LF can operate in 10Base-T full duplex mode.
Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the default
value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last
written value, or the default value if no write has been completed since the last reset.
10Base-T – This bit advertises that the RTL8208B(F)-LF can operate in 10Base-T half duplex mode.
Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the default
value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last
written value, or the default value if no write has been completed since the last reset.
Selector Field – Bits 4:0 contain a fixed value of 00001, indicating that the chip belongs to the
IEEE 802.3 class of PHY transceivers.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
20
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
