RTL8208B-LF/RTL8208BF-LF
Datasheet
5.7. Mode Control Pins
Table 8. Mode Control Pins
Type Description
I/O, Select 10/100BaseTX or 100BaseFX (default = 2’b00).
(Pd, Pd) If PP-LPBK MODE = 0:
2’b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX.
Pin Name
SEL_TXFX[1:0]/
CRS_DV[1:0]
Pin
99, 107
2’b01: Port 7 is 100FX, other ports are 10Base-T/100Base-TX.
2’b10: Ports 6 & 7 are 100FX, other ports are 10Base-T/
100Base-TX.
2’b11: All 8 ports are 100Base-FX.
If PP-LPBK MODE =1:
2’b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX.
2’b01: Port 7 and 5 are 100FX, others are 10Base-T/100Base-TX.
2’b10: Ports 1, 3, 5 & 7 are 100FX, others are
10Base-T/100Base-TX.
2’b11: All 8 ports are 100Base-FX.
Note: RTL8208BF-LF only.
PP-LPBK MODE/
RXD1[0]
105
I/O,
(Pd)
Port-Pair Loopback mode (default =0).
Upon power-on reset, this pin is input to assert PP-LPBK MODE.
When set, all eight ports are port-pair looped back, acting like a signal
regeneration/transformation repeater.
See section 7.1.2 Port Pair-Loop Back Mode (PP-LPBK), page 26,
covering PP-LPBK MODE.
Note: RTL8208BF-LF only.
PHY_ADDR[4:3]/
RXD0[4:3]
77, 84
64, 56
I/O,
PHY Address (default = 2’b01).
(Pd, Pu) These 2 bits determine the highest 2 bits of the 5-bit PHY address
upon reset.
We recommend using a resistor to pull up or pull down.
I/O, (Pu,Pu) Select RMII/SMII/SS-SMII mode (default = 2’b11).
2’b1x: RMII
MODE[1:0]/
CRS_DV[6:7]
2’b00: SMII
2’b01: SS-SMII
We recommend using a resistor to pull up or pull down.
I/O, (Pu) Twisted Pair Pause capability (default =1).
Sets the Flow control ability of Reg.4.10 for UTP ports upon power-
on reset.
1: With flow control ability
0: Without flow control ability
I/O, (Pu) 100Base-FX Flow control capability (default =1).
Forces the flow control capability of Reg.4.10 and Reg.5.10 upon
power-on reset.
TP_PAUSE/
CRS_DV[5]
72
85
FX_PAUSE/
CRS_DV[3]
1: With flow control ability in 100Base-FX
0: Without flow control ability in 100Base-FX
Note: RTL8208BF-LF only.
TP_ASY_PAUSE/
RXD1[5]
70
I/O, (Pd) Twisted Pair Asymmetric Pause capability (default =0).
Sets the Asymmetric Flow control ability of Reg.4.11 for UTP ports
upon power-on reset.
1: With asymmetric flow control ability
0: Without asymmetric flow control ability.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
10
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
