RTL8208B-LF/RTL8208BF-LF
Datasheet
5.3. Miscellaneous Pins
Table 4. Miscellaneous Pins
Pin Name
Pin
Type Description
RESET#
51
I,
Reset.
(Pu)
This is an active low input. To complete the reset function, this pin
must be asserted low for at least 10ms.
25MHz Crystal input or 25MHz Oscillator clock input.
The clock tolerance is ±50ppm.
XI
119
I
When XI is pulled low, XO must be floating. REFCLK will then be
the chip clock input.
XO
REFCLK
120
52
O
I/O
(Pd)
25MHz Crystal output.
Reference clock.
If XI is 25MHz active, REFCLK is a 50MHz output.
If XI is pulled-low (disabled), REFCLK is a clock input as described
below:
RMII mode = 50MHz ±50ppm clock input
SMII/SS-SMII mode = 125MHz ±50ppm clock input.
Pin driver capacity = 8mA.
IBREF
VCTRL
NC
125
126
113
Reference Bias Resistor.
AO
AO
When using a 1:1 transformer on Tx/Rx, this pin must be tied to analog
ground through an external 2KΩ resistor.
Voltage control.
This pin controls a PNP transistor to generate the 1.8V power supply
for VDD and VDDA pins.
Not Connected.
5.4. RMII/SMII/SS-SMII Pins
Table 5. RMII/SMII/SS-SMII Pins
Type Description
I Transmit Data Input (bit 0).
Pin Name
TXD0[7:0]
Pin
58, 66, 74,
80, 87, 95,
101, 109
RMII: TXD0 and TXD1 are the di-bits input, transmitted and driven
synchronously to REFCLK from the MAC.
SMII: TXD0 inputs the data that is transmitted and is driven
synchronously to REFCLK. In 100Mbps, TXD0 inputs a new 10-bit
segment starting with SYNC. In 10Mbps, TXD0 must repeat each
10-bit segment 10 times.
SS-SMII: TXD0 behaves as SMII except synchronous to TX_CLK
instead of REFCLK and inputs a new 10-bit segment starting with
TX_SYNC instead of SYNC.
TXD1[7:0]
57, 65, 73,
79, 86, 94,
100, 108
I
Transmit Data Input (bit 1).
RMII: TXD1 and TXD0 are the input di-bits synchronously to
REFCLK.
SMII/SS-SMII: The I/O pin of TX_EN should not be used.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
7
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
