RTL8201CL
Datasheet
6.2. Register 1 Basic Mode Status Register
Table 10. Register 1 Basic Mode Status Register
Address
Name
Description
Mode
Default
1:15
100Base-T4
1: Enable 100Base-T4 support
0: Suppress 100Base-T4 support
RO
RO
RO
RO
RO
0
1:14
1:13
1:12
1:11
100Base_TX_ FD 1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
100BASE_TX_HD 1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
1
1
1
1
10Base_T_FD
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
10_Base_T_HD
1:10~7
1:6
Reserved
MF Preamble
Suppression
The RTL8201CL will accept management frames with
preamble suppressed.
RO
1
A minimum of 32 preamble bits are required for the first SMI
read/write transaction after reset. One idle bit is required
between any two management transactions as per IEEE 802.3u
specifications.
1:5
1:4
Auto Negotiation 1: Auto-negotiation process completed
RO
RO
0
0
Complete
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band
signal Far-End-Fault has been detected. See 0
Far End Fault Indication, page 22.
1:3
1:2
1:1
1:0
Auto Negotiation 1: Link has not experienced fail state
0: Link experienced fail state
RO
RO
RO
RO
1
0
0
1
Link Status
1: Valid link established
0: No valid link established
1: Jabber condition detected
0: No jabber condition detected
Jabber Detect
Extended Capability 1: Extended register capability
0: Basic register capability only
6.3. Register 2 PHY Identifier Register 1
Table 11. Register 2 PHY Identifier Register 1
Address
Name
Description
Mode
Default
2:15~0
PHYID1
PHY identifier ID for software recognition of the RTL8201CL
RO
0000
6.4. Register 3 PHY Identifier Register 2
Table 12. Register 3 PHY Identifier Register 2
Address
Name
Description
Mode
Default
3:15~0
PHYID2
PHY identifier ID for software recognition of the RTL8201CL
RO
8201
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
9
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
