RTL8201CL
Datasheet
8.2.3. SNI Transmission Cycle Timing
Table 35. SNI Transmission Cycle Timing
Symbol
Description
Minimum
Maximum
Unit
ns
ns
ns
ns
t1
t2
t3
t4
t5
t8
TXCLK high pulse width
TXCLK low pulse width
TXCLK period
TXEN, TXD0 setup to TXCLK rising edge
TXEN, TXD0 hold after TXCLK rising edge
Transmit latency
36
36
80
20
10
120
50
ns
ns
Figure 10 shows an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
IL(max)
TXCLK
V
t1
t2
t5
t4
V
V
TXD0
TXEN
IH(min)
IL(max)
Figure 10. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t8
t9
TPTX+-
Figure 11. SNI Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
27
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
