RTL8169S-32/RTL8169S-64
Datasheet
List of Figures
FIGURE 1. 128-PIN QFP PIN ASSIGNMENTS ................................................................................................................................3
FIGURE 2. 233-PIN TFBGA PIN ASSIGNMENTS ..........................................................................................................................4
FIGURE 3. RX LED...................................................................................................................................................................15
FIGURE 4. TX LED ...................................................................................................................................................................16
FIGURE 5. TX/RX LED.............................................................................................................................................................17
FIGURE 6. LINK/ACT LED......................................................................................................................................................18
FIGURE 7. SERIAL EEPROM INTERFACE TIMING .....................................................................................................................25
FIGURE 8. OUTPUT TIMING MEASUREMENT CONDITIONS .........................................................................................................27
FIGURE 9. INPUT TIMING MEASUREMENT CONDITIONS ............................................................................................................27
FIGURE 10. 3.3V CLOCK WAVEFORM.........................................................................................................................................28
FIGURE 11. CLOCK SKEW DIAGRAM...........................................................................................................................................28
FIGURE 12. I/O READ .................................................................................................................................................................29
FIGURE 13. I/O WRITE................................................................................................................................................................29
FIGURE 14. CONFIGURATION READ ............................................................................................................................................30
FIGURE 15. CONFIGURATION WRITE...........................................................................................................................................31
FIGURE 16. BUS ARBITRATION ...................................................................................................................................................31
FIGURE 17. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT)...........................................................32
FIGURE 18. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) .........................................................33
FIGURE 19. TARGET INITIATED TERMINATION - DISCONNECT....................................................................................................33
FIGURE 20. TARGET INITIATED TERMINATION - ABORT .............................................................................................................34
FIGURE 21. MASTER INITIATED TERMINATION - ABORT.............................................................................................................34
FIGURE 22. PARITY OPERATION – ONE EXAMPLE ......................................................................................................................35
FIGURE 23. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) .........................36
FIGURE 24. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ........................37
FIGURE 25. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)..........................38
FIGURE 26. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ........................39
FIGURE 27. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT).................................................40
FIGURE 28. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) ...............................................40
FIGURE 29. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)................41
FIGURE 30. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ..............42
FIGURE 31. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)................43
FIGURE 32. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ..............44
Integrated Gigabit Ethernet Controller (NIC)
vi
Track ID: JATR-1076-21 Rev. 1.7
REALTEK [ Realtek Semiconductor Corp. ]
