RTL8169S-32/RTL8169S-64
Datasheet
Symbol
Type
Pin No.
(233BGA)
Description
Pin No.
(128QFP)
76
PAR
T/S
M16
Parity. This signal indicates even parity across
PCIADPIN31-0 and CBEB3-0 including the PAR pin. PAR
is stable and valid one clock after each address phase. For
data phase, PAR is stable and valid one clock after either
IRDYB is asserted on a write transaction or TRDYB is
asserted on a read transaction. Once PAR is valid, it remains
valid until one clock after the completion of the current data
phase. As a bus master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read
data phases.
M66EN
PERRB
SERRB
I
88
70
75
F17
P17
N15
66MHZ_ENABLE. This pin indicates to the device whether
the bus segment is operating at 66 or 33MHz. When this pin
(active high) is asserted, the current PCI bus segment that
the device resides on operates in 66MHz mode. If this pin is
de-asserted, the current PCI bus segment operates in
33MHz mode.
Parity Error. This pin is used to report data parity errors
during all PCI transactions except a Special Cycle. PERRB
is driven active (low) two clocks after a data parity error is
detected by the device receiving data, and the minimum
duration of PERRB is one clock for each data phase with
parity error detected.
S/T/S
O/D
System Error. If an address parity error is detected and
Configuration Space Status register bit 15 (detected parity
error) is enabled, the device asserts the SERRB pin low and
bit 14 of the Status register in Configuration Space.
STOPB
S/T/S
I
69
27
T17
L3
Stop. Indicates that the current target is requesting the
master to stop the current transaction.
Reset. When PCIRSTB is asserted low, the device performs
an internal system hardware reset. PCIRSTB must be held
for a minimum period of 120 ns.
PCIRSTB
ACK64B
S/T/S
K2
Acknowledge 64-bit Transfer. When actively driven by a
device that has positively decoded its address as the target
of the current access, indicates the target is willing to
transfer data using 64 bits. ACK64B has the same timing as
DEVSELB.
REQ64B
PAR64
S/T/S
T/S
L2
R2
Request 64-bit Transfer. When asserted by the current bus
master, indicates it desires to transfer data using 64 bits.
REQ64B also has the same timing as FRAMEB.
Parity Upper DWORD. An even parity bit that protects
AD[64:32] and C/BE[7:4]. PAR64 must be valid one clock
after each address phase on any transaction in which
REQ64B is asserted.
Integrated Gigabit Ethernet Controller (NIC)
8
Track ID: JATR-1076-21 Rev. 1.7
REALTEK [ Realtek Semiconductor Corp. ]
