RTL8110SC(L)
Datasheet
6.6. EEPROM Interface
The RTL8110SC(L) requires the attachment of an external EEPROM. The 93C46 is a 1K-bit EEPROM
(the 93C56 is a 2K-bit EEPROM, the 93C66 is a 4K-bit EEPROM). The EEPROM interface provides the
ability for the RTL8110SC(L) to read from and write data to an external serial EEPROM device.
Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be
overridden following a power-on or software EEPROM auto-load command. The RTL8110SC(L) will
auto-load values from the EEPROM. If the EEPROM is not present, the RTL8110SC(L) initialization
uses default values for the appropriate Configuration and Operational Registers. Software can read and
write to the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD. The interface
consists of EESK, EECS, EEDO, and EEDI.
Table 10. EEPROM Interface
EEPROM
EECS
EESK
Description
93C46 (93C56/93C66) chip select.
EEPROM serial data clock.
EEDI/Aux
Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to Boot PROM. To support wakeup from ACPI D3cold
or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this
pin is not pulled high to Aux. Power, the RTL8110SC(L) assumes that no Aux. Power
exists.
EEDO
Output data bus.
6.7. Power Management
The RTL8110SC(L) is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and
Network Device Class Power Management Reference Specification (V1.0a), such as to support an
Operating System-directed Power Management (OSPM) environment.
The RTL8110SC(L) can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and
notify the system via PME# when such a packet or event occurs. Then, the whole system can be restored
to a normal state to process incoming jobs.
When the RTL8110SC(L) is in power down mode (D1 ~ D3):
• The Rx state machine is stopped, and the RTL8110SC(L) monitors the network for wakeup events
such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in
power down mode, the RTL8110SC(L) will not reflect the status of any incoming packets in the ISR
register and will not receive any packets into the Rx FIFO buffer.
• The FIFO status and packets that have already been received into the Rx FIFO before entering power
down mode are held by the RTL8110SC(L).
• Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
• After restoration to a D0 state, the RTL8110SC(L) transfers data that was not moved into the Tx FIFO
buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI) 19
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
