RTL8110SC(L)
Datasheet
6.4. PHY Transceiver
6.4.1. PHY Transmitter
In 10Mbps mode, the Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through
the transmitting physical layer interface. The transmit 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz
(TXC), are serialized into 10Mbps serial data. Then, the 10Mbps serial data is converted into a
Manchester-encoded data stream and is transmitted onto the media by the DAC converter.
In 100Mbps mode, the transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC),
are converted into 5B symbol code via 4B/5B coding technology, scrambling, and serializing before
being converted to 125MHz NRZ and NRZI signals. After that, the NRZI signal is passed to the MLT-3
encoder, then to the DAC converter for transmission onto the media.
In 1000Mbps mode, the RTL8110SC(L)’s PCS layer receives data bytes from the MAC through the
GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding
technology. Then those code groups are passed through a waveform shaping filter to minimize EMI
effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a DAC.
6.4.2. PHY Receiver
In MII (10Mbps) mode, the received differential signal is converted into a Manchester-encoded data
stream. The stream is processed with a Manchester decoder, and is de-serialized into 4-bit wide nibbles.
The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. In 100Mbps mode, the
MLT-3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery,
MLT-3 and NRZI decoder, descrambler, 4B/5B decoder, and then is presented to the MII interface in
4-bit wide nibbles at a clock speed of 25MHz.
In GMII mode, the input signal from the media first passes through the on-chip sophisticated hybrid
circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo.
Afterwards, the received signal is processed with adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. Then the 8-bit wide data is recovered and is sent to the GMII interface at a clock speed of
125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the
Rx Buffer Manager.
6.5. Next Page
If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and
Reg8 as defined in IEEE 802.3ab.
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI) 18
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
