RTL8110S-32/RTL8110S-64
Datasheet
Symbol
Type
Pin No.
Description
Pin No.
(128QFP)
28
(233BGA)
PCICLK
I
M1
PCI clock: This clock input provides timing for all PCI
transactions and is input to the PCI device. Supports up to
a 66MHz PCI clock.
CLKRUNB
I/O
65
T15
Clock Run: This signal is used by the RTL8110S to
request starting (or speeding up) of the PCICLK clock.
CLKRUNB also indicates the clock status. For the
RTL8110S, CLKRUNB is an open drain output as well as
an input. The RTL8110S requests the central resource to
start, speed up, or maintain the interface clock by the
assertion of CLKRUNB. For the host system, it is an
S/T/S signal. The host system (central resource) is
responsible for maintaining CLKRUNB asserted, and for
driving it high to the negated (deasserted) state.
DEVSELB
FRAMEB
S/T/S
S/T/S
68
61
T16
R13
Device Select: As a bus master, the RTL8110S samples
this signal to insure that a PCI target recognizes the
destination address for the data transfer. As a target, the
RTL8110S asserts this signal low when it recognizes its
target address after FRAMEB is asserted.
Cycle Frame: As a bus master, this pin indicates the
beginning and duration of an access. FRAMEB is asserted
low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When
FRAMEB is de-asserted, the transaction is in the final
data phase.
As a target, the device monitors this signal before
decoding the address to check if the current transaction is
addressed to it.
GNTB
I
29
N2
Grant: This signal is asserted low to indicate to the
RTL8110S that the central arbiter has granted the
ownership of the bus to the RTL8110S. This input is used
when the device is acting as a bus master.
REQB
IDSEL
T/S
I
30
46
P2
Request: The RTL8110S will assert this signal low to
request the ownership of the bus from the central arbiter.
U6
Initialization Device Select: This pin allows the device to
identify when configuration read/write transactions are
intended for it.
INTAB
IRDYB
O/D
25
63
K3
Interrupt A: Used to request an interrupt. It is asserted
low when an interrupt condition occurs, as defined by the
Interrupt Status, Interrupt Mask.
Initiator Ready: This indicates the initiating agent’s
ability to complete the current data phase of the
transaction.
S/T/S
R14
As a bus master, this signal will be asserted low when the
device is ready to complete the current data phase
transaction. This signal is used in conjunction with the
TRDYB signal. Data transaction takes place at the rising
edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has
put data on the bus.
Integrated Gigabit Ethernet Controller
7
Track ID: JATR-1076-21 Rev. 1.4
REALTEK [ Realtek Semiconductor Corp. ]
