RTL8110S-32/RTL8110S-64
Datasheet
5.2. PCI Interface
Table 2.
PCI Interface
Symbol
Type
Pin No.
Description
Pin No.
(233BGA)
(128QFP)
PCIADPIN63-32
T/S
T3, R4, U4,
T5, T6, U7,
U8, U9, U11,
U12, U13,
U15, T14,
R12, R15,
U16, U17,
R17, P16,
N16, M17,
M15, K17,
J16, H17,
G17, G15,
F16, E16,
D17, C17,
B17
AD63-32: High 32-bit PCI address and data
multiplexed pins.
Address and Data are multiplexed on the same pins and
provide 32 additional bits. During an address phase (when
using the DAC command and when REQ64B is asserted),
the upper 32-bits of a 64-bit address are transferred;
otherwise, these bits are reserved but are stable and
undetermined. During a data phase, an additional 32-bits
of data are transferred when a 64-bit transaction has been
negotiated by the assertion of REQ64B and ACK64B.
PCIADPIN31-0
T/S
33, 34, 36, T1, T2, U2, AD31-0: Low 32-bit PCI address and data multiplexed
37, 39, 40, R3, T4, U3, pins. The address phase is the first clock cycle in which
42, 43, 47, R5, U5, T7, FRAMEB is asserted. During the address phase, AD31-0
49, 50, 53, T8, T9, T10, contains a physical address (32 bits). For I/O, this is a byte
55, 57, 58,
59, 79, 82,
83, 85, 86,
87, 89, 90,
T11, R9,
address, and for configuration and memory, it is a
T12, U14, double-word address. The RTL8110S supports both
L16, K16, big-endian and little-endian byte ordering. Write data is
J17, J15,
stable and valid when IRDYB is asserted. Read data is
93, 95, 96, H16, G16, stable and valid when TRDYB is asserted. Data I is
97, 98, 102, E17, E15, transferred during those clocks where both IRDYB and
103, 104
C16, A17, TRDYB are asserted.
B16, D15,
A15, C14,
B13, C12
CBEBPIN7-4
CBEBPIN3-0
T/S
T/S
M2, M3, N1, PCI bus command and byte enables multiplexed pins.
R1
During the address phase of a transaction, CBEBPIN7-4
define the bus command. During the data phase,
CBEBPIN7-4 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which
byte lanes carry meaningful data. CBEBPIN4 applies to
byte 4, and CBEBPIN7 applies to byte 7.
44, 60, 77,
92
R6, T13,
PCI bus command and byte enables multiplexed pins.
L17, D16 During the address phase of a transaction, CBEBPIN3-0
define the bus command. During the data phase,
CBEBPIN3-0 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which
byte lanes carry meaningful data. CBEBPIN0 applies to
byte 0, and CBEBPIN3 applies to byte 3.
Integrated Gigabit Ethernet Controller
6
Track ID: JATR-1076-21 Rev. 1.4
REALTEK [ Realtek Semiconductor Corp. ]
