VRS51L1050
Timing Requirement for External Clock (VSS = 0v Assumed)
FIGURE 27: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED)
TCLCL
Vdd - 0.5V
70% Vdd
20% Vdd-0.1V
0.45V
TCLCX
TCHCX
TCHCL
TCLCH
External Program Memory Read Cycle
The following timing diagram provides external program memory read cycle timing information.
FIGURE 28: EXTERNAL PROGRAM MEMORY READ CYCLE
TPLPH
#PSEN
TLLPL
TLHLL
ALE
TPXIZ
TAVLL TLLAX
A0-A7
TPLIV
TPXIX
TPLAZ
TAVIV
Instruction IN
A0-A7
PORT 0
PORT2
P2.0-P2.7 or AB-A15 from DPH
A8-A15
______________________________________________________________________________________________
www.ramtron.com page 44 of 49