VRS51L1050
The transistor will be off (open-circuited) and current
will flow from the VCC to the pin, generating a logical
high at the output. Note that if an external device with a
logical low value is connected to the pin, current will
flow out of the pin.
Input/Output Ports
The VRS51L1050 has 36 bi-directional lines grouped
into four 8-bit I/O ports and one 4-bit I/O port. These
I/Os can be individually configured as inputs or
outputs. The VRS51L1050 I/O pins are not 5V tolerant.
The presence of the pull-up resistance, even when the
I/Os are configured as inputs, means that a small
current is likely to flow from the VRS51L1050 I/O’s
pull-up resistors to the driving circuit when the inputs
are driven low. For this reason, the VRS51L1050 I/O
ports P1, P2, P3 and P4 are called “quasi bi-
directional”.
Except for the P0 I/Os, which are of the open drain
type, each I/O consists of a transistor connected to
ground and a weak pull-up resistor (transistor-based).
Writing a 0 in a given I/O port bit register will activate
the transistor connected to Vss. This will bring the I/O
to a low level.
Structure of Port 0
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case,
an internal weak pull-up resistor will bring the pin to a
high level (except for Port 0 which is open-drain).
The internal structure of P0 is shown in the next figure.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is
configured for accessing external memory/data bus
(EA=0).
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all I/Os are configured as inputs. The VRS51L1050 I/O
ports are not designed to source current.
Structure of the P1, P2, P3 and P4 Ports
When used as an I/O port, P0 acts as an open-drain
port and the use of an external pull-up resistor will
likely be required for most applications.
The following figure provides the general structure of
the P1, P2 and P3 port I/Os. For these ports, the
output stage is composed of a transistor (X1) and a
transistor set configured as a weak pull-up. Note that
the figure below does not show the intermediary logic
that connects the register’s output and the output stage
because this logic varies with the auxiliary function of
each port.
FIGURE 8: PORT P0’S PARTICULAR STRUCTURE
Address A0/A7
Read Register
Control
Vcc
FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2, P3 AND P4
Read Register
Q
Internal Bus
IC Pin
D Flip-Flop
Vcc
X1
Write to
Register
Q
Pull-up
Network
Q
Internal Bus
Read Pin
IC Pin
D Flip-Flop
Write to
Register
X1
Q
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
Read Pin
The bit-addressable P0 register, located at address
80h, controls the P0 pin directions when used as an
I/O (see the following table).
Each I/O may be used independently as a logical
input or output. When used as an input, as mentioned
previously, the corresponding bit register must be high.
This corresponds to #Q=0 in the above figure.
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