VRS51L1050
Exiting Power Down
Power Control Register
The VRS51L1050 features two options for exiting
power down mode:
The VRS51L1050 provides two power saving modes,
idle and power down, which are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
•
•
Hardware Reset
Triggering External Interrupts INT0 or INT1
TABLE 15: POWER CONTROL REGISTER (PCON) - SFR 87H
For the VRS51L1050 to exit power down mode from
an external interrupt (INT0 or INT1), the PDWAKEUP
bit of the SYSCON register must be set to 1 and the
external interrupt must be activated and configured to
be edge or level sensitive.
7
6
5
4
3
2
1
0
SMOD
PDOWN
GF1
GF0
IDLE
Bit
Mnemonic Description
7
SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
Since the oscillator is disabled in power down mode,
when an interrupt is received there will be a delay
before the system restarts. The length of the delay
before the device exits power down mode will be 65-
75K oscillator cycles, may vary from device to device
and depends on the crystal used (approximately 3.1ms
for a 22.1184MHz crystal and 6.2ms for a 11.0592MHz
crystal).
6
5
4
3
2
1
0
GF1
GF0
PDOWN
IDLE
General Purpose Flag
General Purpose Flag
Power down mode control bit
Idle mode control bit
When the VRS51L1050 exits power down mode as a
result of an external interrupt, the program counter will
jump to its associated interrupt service routine. Upon
completion of the interrupt service routine, the
processor will return to the main program and execute
the next instruction following the one that put the
device into power down mode. When the VRS51L1050
is in power down mode, its current consumption drops
below 20uA.
The SMOD bit of the PCON register controls the
oscillator divisor applied to Timer 1 when used as a
baud rate generator for the UART. Setting this bit to 1
doubles the UART’s baud rate generator frequency.
In idle mode, the processor is disabled and the
oscillator continues operating. The contents of the
SRAM, I/O state and SFR registers are maintained and
the timer and external interrupts remain operational.
The processor will be woken up when an external
event, triggering an interrupt, occurs.
In power down mode, the oscillator and peripherals are
disabled. The contents of the SRAM and the SFR
registers, however, are maintained.
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