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VRS51C1000-40-PG 参数 Datasheet PDF下载

VRS51C1000-40-PG图片预览
型号: VRS51C1000-40-PG
PDF下载: 下载PDF文件 查看货源
内容描述: 的Versa 8051 MCU与IAP / ISP功能的Flash 64KB [Versa 8051 MCU with 64KB of IAP/ISP Flash]
分类和应用: 微控制器和处理器
文件页数/大小: 48 页 / 475 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号VRS51C1000-40-PG的Datasheet PDF文件第34页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第35页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第36页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第37页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第39页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第40页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第41页浏览型号VRS51C1000-40-PG的Datasheet PDF文件第42页  
VRS51C1000  
AC Characteristics  
TABLE 48: AC CHARACTERISTICS  
Fosc 16  
Variable Fosc  
Valid  
Symbol  
T LHLL  
T AVLL  
T LLAX  
T LLIV  
T LLPL  
T PLPH  
T PLIV  
Parameter  
ALE Pulse Width  
Cycle  
Unit  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
Min.  
Type Max.  
Min.  
Type  
Max.  
RD/WRT 115  
RD/WRT 43  
RD/WRT 53  
RD  
2xT - 10  
T - 20  
T - 10  
Address Valid to ALE Low  
Address Hold after ALE Low  
ALE Low to Valid Instruction In  
ALE Low to #PSEN low  
#PSEN Pulse Width  
#PSEN Low to Valid Instruction In  
Instruction Hold after #PSEN  
Instruction Float after #PSEN  
Address to Valid Instruction In  
#PSEN Low to Address Float  
#RD Pulse Width  
240  
177  
4xT - 10  
3xT -10  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
WRT  
RD  
RD  
RD  
RD  
RD  
RD/WRT 178  
RD/WRT 230  
WRT  
WRT  
WRT  
RD  
53  
173  
T - 10  
3xT - 15  
T PXIX  
T PXIZ  
0
0
87  
292  
10  
T + 25  
5xT - 20  
10  
T AVI V  
T PLAZ  
T RLRH  
T WLWH  
T RLDV  
T RHDX  
T RHDZ  
T LLDV  
T AVDV  
T LLYL  
T AVYL  
T QVWH  
T QVWX  
T WHQX  
T RLAZ  
T YALH  
T CHCL  
T CLCX  
T CLCH  
T CHCX  
365  
365  
6xT - 10  
6xT - 10  
#WR Pulse Width  
#RD Low to Valid Data In  
Data Hold after #RD  
302  
5xT - 10  
0
0
Data Float after #RD  
145  
590  
542  
197  
2xT + 20  
8xT - 10  
9xT - 20  
3xT + 10  
ALE Low to Valid Data In  
Address to Valid Data In  
ALE low to #WR High or #RD Low  
Address Valid to #WR or #RD Low  
Data Valid to #WR High  
Data Valid to #WR Transition  
Data Hold after #WR  
#RD Low to Address Float  
#W R or #RD High to ALE High  
Clock Fall Time  
3xT - 10  
4xT - 20  
7xT - 35  
T - 25  
403  
38  
73  
T + 10  
5
RD/WRT 53  
72  
T -10  
T+10  
Clock Low Time  
Clock Rise Time  
Clock High Time  
T,TCLCL Clock Period  
63  
1/fosc  
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