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SM8M72ALDT-7.5 参数 Datasheet PDF下载

SM8M72ALDT-7.5图片预览
型号: SM8M72ALDT-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 8MX72, 4.5ns, CMOS, DIMM-168]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 15 页 / 197 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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168-pin Low Profile ESDRAM DIMMs  
32MB, 64MB, 128MB  
Preliminary Data Sheet  
Read and Write Parameters  
Symbol  
Parameter  
-6  
-7.5  
Units  
Notes  
Min  
-
Max  
Min  
-
Max  
tAC3  
tAC2  
tAC1  
tOH3  
tOH2  
tOH1  
tLZ  
Clock Access Time, CL = 3  
Clock Access Time, CL = 2  
Clock Access Time, CL = 1  
Data Output Hold Time (CL=3)  
Data Output Hold Time (CL=2)  
Data Output Hold Time (CL=1)  
Data Output to Low-Z Time  
Data Output to High-Z Time (CL=2, 3)  
Data Output to High-Z Time (CL=1)  
DQM Data Output Disable Time  
Data Input Set-Up Time  
4.3  
4.5  
ns  
ns  
1,2  
1,2  
1,2  
-
4.6  
-
4.8  
-
10.5  
-
11  
ns  
2.0  
2.3  
3.0  
0
-
2.0  
2.3  
3.0  
0
-
ns  
-
-
ns  
-
-
ns  
-
-
ns  
tHZ2  
tHZ1  
tDQZ  
tDS  
-
4.6  
-
4.8  
ns  
3
3
-
7.0  
-
7.5  
ns  
2
-
-
-
-
-
-
2
-
-
-
-
-
-
CLK  
ns  
1.5  
0.8  
6.0  
20.0  
0
1.5  
0.8  
7.5  
22.5  
0
tDH  
Data Input Hold Time  
ns  
tDPL  
tDAL  
Data Input to Precharge  
ns  
Data Input to ACTV/Refresh  
Data Write Mask Latency  
ns  
tDQW  
CLK  
Notes:  
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.  
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.  
3. Referenced to the time at which the output achieves an open circuit condition.  
Refresh Parameters  
Symbol  
Parameter  
-6  
-7.5  
Units  
Notes  
Min  
-
Max  
64  
Min  
-
Max  
64  
-
tREF  
Refresh Period  
Self Refresh Exit Time  
ms  
ns  
1,2  
3
tSREX  
2CLK+tRC  
2CLK+tRC  
Notes:  
1. 4096 cycles.  
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.  
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not  
completed until tRC is satisfied once the Self-Refresh Exit command is registered.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
2001 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.0  
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