168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
AC Operating Conditions (TA = 0°C to 70°C)
Clock and Clock Enable Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
6.0
12
2.4
5
Max
Min
7.5
15
2.8
6
Max
tCK2
tCK1
Clock Cycle Time, CL = 2, 3
Clock Cycle Time, CL = 1
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tCKH2, tCKL2 Clock High & Low Times, CL=2, 3
tCKH1, tCKL1 Clock High & Low Times, CL=1
-
-
1
1
-
-
tCKES
tCKEH
tCKSP
Clock Enable Set-Up Time
1.5
0.8
1.5
-
-
1.5
0.8
1.5
-
-
Clock Enable Hold Time
-
-
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
-
-
tT
2
3
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-6
-7.5
Units
Notes
Min
1.5
0.8
12
30
18
12
12
6
Max
Min
1.5
0.8
15
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
-
ns
ns
tCH
-
-
tRCD
tRC
tRAS
tRP
-
-
ns
Bank Cycle Time
-
37.5
22.5
15
-
ns
Bank Active Time
120K
120K
ns
Precharge Time
-
-
-
-
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
15
ns
7.5
2
ns
2
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 10 of 15
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
