64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
A write with auto-precharge is no different than issuing a Precharge command directly to the device. The ESDRAM
enters precharge one clock cycle (in this case referred to as tDPL) after the last write burst. The bank being auto-precharged
cannot be reactivated until the data-in to active delay (tDAL = tDPL + tRP) is satisfied. In write with auto-precharge operation,
including full page bursts, the device auto-precharges when any of four commands are issued: Precharge, Burst Stop,
Read to another bank, or Write to another Bank.
Precharge Command
The Precharge command is issued by holding CS#, RAS#, and WE# low and CAS# high at the rising edge of the clock.
This command precharges (closes) a specified bank, or all banks at once. Single banks are specified using BA1 and BA0
while A10/AP is low. All banks are precharged if A10/AP is high. The Precharge command terminates a read after a delay
equal to the CAS latency and a write in the current cycle.
During reads when CAS latency equals one the Precharge command may be applied on the last clock of the burst. During
reads when CAS latency equals two the Precharge command may be applied on the second to last clock of the burst.
During reads when CAS latency equals three the Precharge command may be applied on the third to last clock of the
burst. If a Precharge command is issued any sooner, it terminates the burst as explained in the Read Command section.
During writes a data-in to precharge delay (tDPL) from the last clock of the burst must be satisfied before a Precharge
command can be issued. If a Precharge command is issued any sooner, it terminates the burst as explained in the Write
Command section.
After a Precharge command is issued, the precharged bank must be reactivated before a new Write command can be
executed. The minimum delay between a Precharge command and the Bank Activate command must satisfy the precharge
time (tRP).
Auto Refresh Command (CAS before RAS Refresh)
The Auto-Refresh command (CBR) is issued by holding CS#, RAS#, and CAS# low and CKE, and WE# high at the rising
edge of the clock. All banks must be precharged before this command is issued. The contents of each row cache are
maintained during auto-refresh, so reads may continue. Once the Auto-Refresh command is issued, the next Bank
Activate command can be issued after a delay of at least the RAS cycle time (tRC).
Self Refresh Command
The Self Refresh command is issued by holding CS#, RAS#, CAS#, and CKE low and WE# high at the rising edge of the
clock. Refresh cycles are generated by an internal clock as long as CKE is clocked low. All inputs are disabled except
CKE, and the device is placed in a low power standby mode. The external clock may be stopped during this operation, but
must be cycling upon exit. The ESDRAM exits self refresh on the second rising edge of the clock after CKE is returned
high. The next Bank Activate command can be issued after a delay of at least the RAS cycle time (tRC).
No Operation Command
The No Operation command (NOP) is issued by holding CS# low and RAS#, CAS#, and WE# high at the rising edge of
the clock. The purpose of the NOP is to prevent the ESDRAM from registering any unwanted commands. A NOP does
not terminate any pending operations.
Deselect Command
The Deselect command is issued when CS# is high at the rising edge of clock. This command performs the same function
as a NOP. A Deselect command does not terminate any pending operations.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
Page 13 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
