64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
The minimum time interval between interleaved Bank Activate commands is the bank-to-bank delay time (tRRD).
Read Command
The Read command is initiated by holding CS# and CAS# low and RAS# and WE# high at the rising edge of the clock.
The address inputs determine the starting address for the read. The Mode register settings determine burst type (sequential
or interleaved), burst length (1, 2, 4, 8, full page), and CAS latency (the delay from command start to data output). The
first Read command issued after a Bank Activate command automatically loads the row cache.
If the data mask is activated (DQM high) during a read cycle, the corresponding data outputs are disabled and become
high impedance after a one or two clock delay determined by the programmed DQM latency. Please refer to the Extended
Mode Register Set Command section for setting DQM latency.
Read Interrupted by a Read
A read burst may be interrupted before completion of the burst by another Read command. The data from the first Read
command continues to appear at the outputs until the CAS latency for the new command is satisfied. If the new read is to
a different row, the DRAM array must be precharged and reactivated between the first and the interrupting Read
command, so the new row is loaded into the row cache.
Read Interrupted by a Write
A read burst may be interrupted before completion of the burst by a Write command. DQM must be used to avoid data
contention on the I/O bus by placing the output drivers (DQ15-DQ0) in a high impedance state at least one clock cycle
before initiating the Write command. DQM must go high at least two clock cycles before the Write command, and must
be low in the same clock cycle as the Write command.
The ESDRAM allows the user to close the page being read, to open a different page for the write, and still read data from
the row cache. To write to the same page, a Bank Activate command must be issued before the interrupting Write
command can reopen the closed page.
Read Interrupted by a Precharge
A read burst may be terminated by a Precharge command. The data from the Read command continues to appear at the
outputs until a delay equal to the CAS latency is satisfied. A Precharge command to one bank does not terminate a read
burst from another bank.
Write Command
The Write command is initiated by holding CS#, CAS#, and WE# low and RAS# high at the rising edge of the clock. The
address inputs determine the starting address. There is no CAS latency required for write cycles. Data for the first write
must be supplied on the same clock cycle as the Write command. For bursting, remaining data inputs must be supplied on
each subsequent rising clock edge.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
Page 11 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
