16Mbit ESDRAM Family
Clock Frequency and Latency (-6ns Speed Bin)
Symbol
t
CK
t
AA
t
RCD
t
RL
t
RC
t
RAS
t
RP
t
DPL
t
DAL
t
RRD
t
CCD
Parameter
Clock Cycle Time
CAS Latency
RAS to CAS Delay
RAS Latency
Bank Cycle Time
Minimum Bank Active Time
Precharge Time
Data-In to Precharge Time
Data-In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
66
15
1
1
2
3
2
1
1
2
1
1
Clock Frequency (MHz)
83
100
133
12
10
7.5
1
2
2
1
2
2
2
4
4
3
4
5
2
3
3
2
2
2
1
1
1
3
3
3
1
2
2
1
1
1
166
6.0
2
2
4
6
4
3
2
4
2
1
Units
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
Performance Comparison at 133MHz (ESDRAM vs. SDRAM*)
Page Open
Read Page Hit
Read Page Miss
Write Page Hit
Write Page Miss
ESDRAM
2-1-1-1
6-1-1-1
1-1-1-1
5-1-1-1
SDRAM
4-1-1-1
8-1-1-1
1-1-1-1
9-1-1-1
Page Closed
ESDRAM
SDRAM
2-1-1-1
illegal
4-1-1-1, 2-1-1-1
7-1-1-1, 9-1-1-1
illegal
illegal
2-1-1-1, 5-1-1-1
3-1-1-1, 9-1-1-1
* Assumes SDRAM has fast enough clock access time to satisfy 133MHz system bus.
7
Rev. 2.2
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
