16Mbit ESDRAM Family
Clock Frequency
The following table specifies the operation of the ESDRAM at clock rates ranging from 66MHz to 166MHz. Clock rates
up to 133MHz assume the use of LVTTL I/O levels. Clock rates from 133MHz to 166MHz assume the use of 2.5V I/O
levels.
ESDRAM input setup time is 2ns at 133MHz. ESDRAM clock to output delay is 4.5ns at 133MHz. These improved I/O
specifications allow ESDRAM to operate in real systems at the specified clock rate.
AC Parameters
-6
Symbol
t
CK2
t
CK1
t
AC2
t
AC1
t
CKH2
t
CKH1
t
CKL2
t
CKL1
t
CKES
t
CKEH
t
CKSP
t
T
Parameter
Clock Cycle Time, CL = 2, 3
Clock Cycle Time, CL = 1
Clock Access Time, CL = 2, 3
Clock Access Time, CL = 1
Clock High Time (CL=2,3)
Clock High Time (CL=1)
Clock Low Time (CL=2,3)
Clock Low Time (CL=1)
Clock Enable Set-Up Time
Clock Enable Hold Time
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
Min
6
12
-
-
2.4
5
2.4
5
2.0
1.0
2.0
-
Max
166MHz
83MHz
4.3
10.5
-
-
-
-
-
-
-
3
Min
7.5
15
-
-
2.8
6
2.8
6
2.0
1.0
2.0
-
-7.5
Max
133MHz
66MHz
4.5
12
-
-
-
-
-
-
-
4
Min
10
20
-
-
3.5
7
3.5
7
2.5
1.0
2.5
-
-10
Max
100MHz
50MHz
5
15
-
-
-
-
-
-
-
4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock and Clock Enable Parameters
Common Parameters
t
CS
t
CH
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
Bank Cycle Time
Bank Active Time
Precharge Time
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
2.0
1.0
12
36
18
14
12
6
-
-
-
120K
120K
-
-
-
2.0
1.0
15
37.5
22.5
15
15
7.5
-
-
-
120K
120K
-
-
-
2.5
1.0
20
50
30
20
20
10
-
-
-
120K
120K
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Read and Write Parameters
t
OH2
t
OH1
t
LZ
t
HZ2
t
HZ1
t
DQZ
t
DS
t
DH
t
DPL
t
DAL
t
DQW
Data Output Hold Time (CL=2,3)
Data Output Hold Time (CL=1)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2,3)
Data Output to High-Z Time (CL=1)
DQM Data Output Disable Time
Data Input Set-Up Time
Data Input Hold Time
Data Input to Precharge
Data Input to ACTV/Refresh
Data Write Mask Latency
2
3
0
-
-
2
2.0
1.0
8
22
0
-
-
-
4.3
7.0
-
-
-
-
-
-
2
3
0
-
-
2
2.0
1.0
9
24
0
-
-
-
4.5
7.5
-
-
-
-
-
-
2
3
0
-
-
2
2.5
1.0
10
30
0
-
-
-
5.0
8.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
CLK
ns
ns
ns
ns
CLK
Refresh Parameters
t
REF
t
SREX
Refresh Period (2048 cycles)
Self Refresh Exit Time
-
2CLK
+t
RC
64
-
-
2CLK
+t
RC
64
-
-
2CLK
+t
RC
64
-
ms
ns
6
Rev. 2.2
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
