Preliminary Data Sheet
168-pin Low Profile ESDRAM DIMMs
32MB, 64MB, 128MB
AC Characteristics (T
A
= 0°C to 70°C)
1.
2.
An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum
of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the V
TT
= 1.4V crossover point.
t
T
Clock
t
SETUP
Input
t
AC
t
LZ
Output
t
OH
V
TT
VIH
VTT
VIL
V
TT
R
T
= 50 ohm
Z
0
= 50 ohm
Output
C
LOAD
= 50pF
t
HOLD
AC Output Load Circuit
3.
4.
5.
The transition time is measured between V
IH
and V
IL
(or between V
IH
and V
IL
).
AC measurements assume t
T
= 1ns.
In addition to meeting the transition rate specification, the clock and CKE must transition V
IH
and V
IL
(or between V
IH
and V
IL
) in
a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 9 of 15
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
