168-pin Low profile ESDRAM DIMMs
32MB, 64MB, 128MB
Preliminary Data Sheet
Serial Presence Detect (SPD) for ESDRAM DIMMs
32MB
64MB
128MB
32MB
64MB
128MB
Byte Description
** Hex Code **
0
1
2
3
4
5
6
Number of bytes written into EEPROM
128
256
SDRAM
12
8
1
x64
128
256
SDRAM
12
9
1
x64
x72
128
256
SDRAM
12
9
2
x64
x72
80
08
04
0C
08
01
40
80
80
08
04
0C
09
02
40
48
00
01
60
43
00
02
80
08
00
08
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
12
10
15
08
15
08
00
01
12
46
58
Total number of SPD bytes
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of Module Banks
Module Data Width
08
04
0C
09
01
40
48
00
01
60
43
00
02
80
08
00
08
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
x64
x72
7
8
Module Data Width (cont’d)
Voltage Interface Levels
0
0
0
00
01
60
43
00
LVTTL
6.0 ns
4.3 ns
LVTTL
6.0 ns
4.3 ns
--- Non-parity ---
--- ECC ---
--- 15.625us / Self ---
LVTTL
6.0 ns
4.3 ns
9
10
11
Cycle Time at max CAS Latency
SDRAM Clock Access Time
DIMM config (non-parity, parity, ECC)
12
13
14
Refresh Rate and Type
Primary SDRAM Width
Error Checking Data Width
80
10
00
x16
N/A
x8
N/A
x8
1 clk
x8
N/A
x8
x64
x72
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Min. CAS-to-CAS Delay (tCCD)
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
CS Latency
1 clk
1 clk
01
8F
04
07
01
01
00
07
60
46
30
2A
0C
0C
0C
12
08
15
08
15
08
00
01
12
44
--- 1,2,4,8,Full Pg ---
4
1,2,3
0
4
4
1,2,3
0
1,2,3
0
0
Write Latency
0
0
SDRAM Module Attributes
SDRAM Device Attributes
Min. Clock Cycle Time at CL=2
Clock Access Time at CL=2 (tAC2)
Min. Clock Cycle Time at CL=1
Clock Access Time at CL=1 (tAC1)
Min. Row Precharge Time (tRP)
Min. Row-to-Row Delay (tRRD)
Min. RAS-to-CAS Delay (tRCD)
Min. RAS Pulse Width (tRAS)
Density of each bank on module
Cmd/Addr input set-up time
Cmd/Addr input hold time
Data input set-up time
--- Unbuffered ---
+/-10% Vdd, Precharge All
6 ns
6 ns
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
32MB
6 ns
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
64MB
1.5 ns
0.8 ns
1.5 ns
0.8 ns
-
4.6 ns
12 ns
10.5 ns
12 ns
12 ns
12 ns
18 ns
64MB
12
10
15
08
15
08
00
01
Data input hold time
36-60 Superset Information
-
-
61
62
63
Superset Information (cont’d)
SPD Rev.
Checksum for bytes 0-62
ESDRAM defined for Code=01
1.2
-
12
45
57
non-ECC
ECC
-
-
-
-
64-71 JEDEC ID code
Enhanced Memory Systems
-
7F32FFFFFFFFFFFF
72
Manufacturing Location
xxxx
xxxx
xxxx
xxxx
xxxx
rrrr
yyww
ssss
00
xxxx
xxxx
xxxx
rrrr
yyww
ssss
00
73-90 Manufacturer's Part #
x64
x72
SM4M64ALDT SM8M64ALDT SM16M64ALDT
SM8M72ALDT SM16M72ALDT
91,92 PCB Rev. Code
93,94 Manufacturing Date
95-98 Assembly Serial #
99-125 Manufacturer's Specific Data
126 Intel specification frequency
-
rrrr
yyww
ssss
00
yyww code
serial number
open
100MHz
64
64
64
127 Intel specification CL and clock support
128-255 Open for Customer Use
-
-
-
-
-
-
AF
00
AF
00
FF
00
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 12 of 15
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
