FM33256/FM3316 SPI Companion w/ FRAM
Backup Power
The user will not be able to see the effect of the
calibration setting on the 512 Hz output. The
addition or subtraction of digital pulses occurs after
the 512Hz output.
The real-time clock and alarm are intended to be
permanently powered. When the primary system
power fails, the voltage on the VDD pin will drop.
When the VDD voltage is less than VSW, the RTC
(and event counter) will switch to the backup power
supply on VBAK. The clock operates at extremely
low current in order to maximize battery or capacitor
life. However, an advantage of combining a clock
function with FRAM memory is that data is not lost
regardless of the backup power source.
The calibration setting is stored in FRAM so it is not
lost should the backup source fail. It is accessed with
bits CAL.4-0 in register 01h. This value only can be
written when the CAL bit is set to a 1. To exit the
calibration mode, the user must clear the CAL bit to a
logic 0. When the CAL bit is 0, the ACS pin will
revert to the function according to Table 2.
Trickle Charger
To facilitate capacitor backup, the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit (register 18h bit 3) is set to a ‘1’, the VBAK
pin will source approximately 80 µA until VBAK
reaches VDD. This charges the capacitor to VDD
without an external diode and resistor charger.
There is a Fast Charge mode which is enabled by the
FC bit (register 18h, bit 2). In this mode the trickle
charger current is set to approximately 1 mA,
allowing a large backup capacitor to charge more
quickly.
Crystal Type
The crystal oscillator is designed to use a 12.5pF
crystal without the need for external components,
such as loading capacitors. The FM33xx device has
built-in loading capacitors that match the crystal.
If a 32.768kHz crystal is not used, an external
oscillator may be connected to the FM33xx. Apply
the oscillator to the X1 pin. Its high and low voltage
levels can be driven rail-to-rail or amplitudes as low
as approximately 500mV p-p. To ensure proper
operation, a DC bias must be applied to the X2 pin.
It should be centered between the high and low levels
on the X1 pin. This can be accomplished with a
voltage divider.
•
In the case where no battery is used, the VBAK
pin should be tied to VSS.
! Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 KΩ series
resistor as a safety element.
Vdd
FM33xx
R1
Calibration
When the CAL bit in register 00h is set to a ‘1’, the
clock enters calibration mode. The FM33xx devices
employ a digital method for calibrating the crystal
oscillator frequency. The digital calibration scheme
applies a digital correction to the RTC counters based
on the calibration settings, CALS and CAL.4-0. In
calibration mode (CAL=1), the ACS pin is driven
with a 512 Hz (nominal) square wave and the alarm
is temporarily unavailable. Any measured deviation
from 512 Hz translates into a timekeeping error. The
user measures the frequency and writes the
appropriate correction value to the calibration
register. The correction codes are listed in the table
below. For convenience, the table also shows the
frequency error in ppm. Positive ppm errors require a
negative adjustment that removes pulses. Negative
ppm errors require a positive correction that adds
pulses. Positive ppm adjustments have the CALS
(sign) bit set to 1, where as negative ppm adjustments
have CALS = 0. After calibration, the clock will have
a maximum error of ± 2.17 ppm or ± 0.09 minutes
per month at the calibrated temperature.
X2 X1
R2
Figure 10. External Oscillator
In the example, R1 and R2 are chosen such that the
X2 voltage is centered around the oscillator drive
levels. If you wish to avoid the DC current, you may
choose to drive X1 with an external clock and X2
with an inverted clock using a CMOS inverter.
Layout Recommendations
The X1 and X2 crystal pins employ very high
impedance circuits and the oscillator connected to
these pins can be upset by noise or extra loading. To
reduce RTC clock errors from signal switching noise,
a guard ring should be placed around these pads and
the guard ring grounded. High speed SPI traces
should be routed away from the X1/X2 pads. The X1
and X2 trace lengths should be less than 5 mm. The
Rev. 1.0
Dec. 2006
Page 9 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
