FM33256/FM3316 SPI Companion w/ FRAM
Table 3. Alarm Match Bit Examples
Seconds Minutes Hours Date Months Alarm condition
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
No match required = alarm 1/second
Alarm when seconds match = alarm 1/minute
Alarm when seconds, minutes match = alarm 1/hour
Alarm when seconds, minutes, hours match = alarm 1/date
Alarm when seconds, minutes, hours, date match = alarm 1/month
read by the user. If a timekeeper update is pending
when R is set, then the core will be updated prior to
loading the user registers. The user registers are
frozen and will not be updated again until the R bit is
cleared to a ‘0’.
Real-time Clock Operation
The real-time clock (RTC) is a timekeeping device
that can be capacitor- or battery-backed for
permanently-powered operation. It offers a software
calibration feature that allows high accuracy.
The W bit is used to write new time/date values.
Setting the W bit to a ‘1’ stops the RTC and allows
the timekeeping core to be written with new data.
Clearing it to ‘0’ causes the RTC to start running
based on the new values loaded in the timekeeper
core. The RTC may be synchronized to another clock
source. On the 8th clock of the write to register 00h
(W=0), the RTC starts counting with a timebase that
has been reset to zero milliseconds.
The RTC consists of an oscillator, clock divider, and
a register system for user access. It divides down the
32.768 kHz time-base and provides a minimum
resolution of seconds (1Hz). Static registers provide
the user with read/write access to the time values. It
includes registers for seconds, minutes, hours, day-
of-the-week, date, months, and years. A block
diagram shown in Figure 9 illustrates the RTC
function.
Note: Users should be certain not to load invalid
values, such as FFh, to the timekeeping registers.
Updates to the timekeeping core occur continuously
except when locked.
The user registers are synchronized with the
timekeeper core using R and W bits in register 00h.
The R bit is used to read the time. Changing the R bit
from 0 to 1 transfers timekeeping information from
the core into the user registers 02-08h that can be
512 Hz or
SW out
/OSCEN
Oscillator
W
Clock
Divider
Update
Logic
32.768 kHz
crystal
1 Hz
Years
8 bits
Months
5 bits
Date
6 bits
Hours
6 bits
Minutes
7 bits
Seconds
7 bits
CF
Days
3 bits
R
User Registers
Figure 9. Real-time Clock Core Block Diagram
Rev. 1.0
Dec. 2006
Page 8 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
