FM3130 Integrated RTC/Alarm with 64Kb FRAM
AC Test Conditions
Equivalent AC Test Load Circuit
3.6V
Input Pulse Levels
0.1 VDD to 0.9 VDD
10 ns
Input rise and fall times
Input and output timing levels
0.5 VDD
1100
Ω
Diagram Notes
Output
All start and stop timing parameters apply to both read and write
cycles. Clock specifications are identical for read and write cycles.
Write timing parameters apply to slave address, word address, and
write data bits. Functional relationships are illustrated in the relevant
data sheet sections. These diagrams illustrate the timing parameters
only.
100 pF
Read Bus Timing
tHIGH
tR
tSP
tF
t SP
tLOW
`
SCL
1/fSCL
tSU:STA
tHD:DAT
tSU:DAT
tBUF
SDA
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Power Cycle Timing
VDD
2.7V
tRPU
Can user
access device?
no
yes
yes
Rev. 1.0
Sept. 2006
Page 19 of 22
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
