FM3130 Integrated RTC/Alarm with 64Kb FRAM
Stop
Start
S
Address & Data
Address MSB
By Master
0
A
A
A
A
P
Slave Address
Address LSB
Data Byte
By FM3130
Acknowledge
Figure 7. Single Byte Memory Write
Start
S
Stop
P
Address & Data
Address MSB
By Master
0
A
A
A
A
A
Slave Address
Address LSB
Data Byte
Data Byte
By FM3130
Acknowledge
Figure 8. Multiple Byte Memory Write
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM3130 attempts to
read out additional data onto the bus. The four valid
methods follow.
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM3130 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
1. The bus master issues a NACK in the 9th clock
cycle and a Stop in the 10th clock cycle. This is
illustrated in the diagrams below and is
preferred.
Current Address & Sequential Read
2. The bus master issues a NACK in the 9th clock
cycle and a Start in the 10th.
As mentioned above the FM3130 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
3. The bus master issues a Stop in the 9th clock
cycle.
4. The bus master issues a Start in the 9th clock
cycle.
If the internal address reaches the top of memory, it
will wrap around to 0000h on the next read cycle.
The figures below show the proper operation for
current address reads.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM3130
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM3130 acknowledges the address, the bus master
Each time the bus master acknowledges a byte,
this indicates that the FM3130 should read out
the next sequential byte.
Rev. 1.0
Sept. 2006
Page 14 of 22
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
