FM28V100 - 128Kx8 FRAM
Address Latch
Row Decoder
A(16:3)
A(16:0)
16K x 64
F-RAM Array
A(2:0)
...
CE1, CE2
2
WE
OE
Control
Logic
Column Decoder
I/O Latch & Bus Driver
DQ(7:0)
Figure 1. Block Diagram
Pin Descriptions
Pin Name
Type
A(16:0)
Input
/CE1, CE2
Input
/WE
Input
/OE
DQ(7:0)
NC
VDD
VSS
Input
I/O
-
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of
CE2 (while /CE1 low). Addresses A(2:0) are used for page mode read and write operations.
Chip Enable inputs: The device is selected and a new memory access begins on the falling
edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The entire
address is latched internally at this point. The CE2 pin is pulled up internally.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM28V100 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for fast page mode write cycles.
Output Enable: When /OE is low, the FM28V100 drives the data bus when valid data is
available. Deasserting /OE high tri-states the DQ pins.
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
No Connect: This pin has no internal connection.
Supply Voltage
Ground
Rev. 1.2
May 2010
Page 2 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
