FM25V02 - 256Kb SPI FRAM
S
C
. . . . . . .
Byte 6
D
Q
C3h
Byte 7
. . .
Byte 1
Byte 0
Figure 15. Read Serial Number
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 40MHz clock rate.
Endurance
The FM25V02 and FM25VN02 devices are capable
of being accessed at least 1014 times, reads or writes.
An F-RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A14-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 4K rows of
Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop
SCK Freq Endurance Endurance Years to Reach
(MHz) Cycles/sec.
Cycles/year
1014 Cycles
40
20
10
5
74,620
37,310
18,660
9,330
2.35 x 1012
1.18 x 1012
5.88 x 1011
2.94 x 1011
42.6
85.1
170.2
340.3
Rev. 2.0
May 2010
Page 11 of 17
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
