FM25L256 Extended Temp.
AC Parameters (TA = -25° C to +85° C, VDD = 3.0V to 3.6V, CL = 30pF)
Symbol
Parameter
Min
Max
Units
Notes
fCK
tCH
tCL
tCSU
tCSH
tOD
tODV
tOH
tD
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
0
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
22
10
10
1
1
20
22
2
0
60
tR
tF
Data In Rise Time
Data In Fall Time
Data Setup Time
50
50
1,3
1,3
tSU
tH
tHS
tHH
tHZ
tLZ
5
5
10
10
Data Hold Time
D
/Hold Setup Time
/Hold Hold Time
/Hold Low to Hi-Z
/Hold High to Data Active
ns
E
ns
20
20
2
2
ns
D
Notes
1. tCH + tCL = 1/fCK
2. This parameter is characterized but not 100% tested.
3. Rise and fall times measured between 10% and 90% of waveform.
S
.
N
N
Power Cycle Timing (TA = -25° C to +85° C, VDD = 3.0V to 3.6V)
Symbol
G
Units
ms
ME
I
Parameter
Min
Max
Notes
B
tPU
tPD
tVR
tVF
Power Up (VDD min) to First Access (/CS low)
Last Access (/CS high) to Power Down (VDD min)
VDD Rise Time
10
0
50
-
S
6
M
-
-
-
5
µ
s
5
µs/V
µs/V
1,2
1,2
E
2
O
VDD Fall Time
100
L
D
Notes
C
1. Slope measured at any point on VDD waveform.
2
2. Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
E
M
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
W
F
R
:
E
e
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
v Min
Parameter
i
t
Max
Units
Notes
T
N
CO
CI
Output Capacitance (SO)
-
-
8
6
pF
pF
1
1
a
Input Capacitance
O
n
r
R
Notes
e
ThisNparameter is characterized and not 100% tested.
1.
t
l
O
A
F
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Rev. 2.3
March 2007
Page 10 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
