FM25H20 - 2Mb SPI FRAM
Power Up to First Access
The FM25H20 is not accessible for a period of time
(1 ms) after power up. Users must comply with the
timing parameter t
PU
, which is the minimum time
from V
DD
(min) to the first /S low.
Data Transfer
All data transfers to and from the FM25H20 occur in
8-bit groups. They are synchronized to the clock
signal (C), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of C. Outputs are driven from the falling edge of
C.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25H20. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE
Write Memory Data
Enter Sleep Mode
SLEEP
Op-code
0000
0000
0000
0000
0000
0000
1011
0110b
0100b
0101b
0001b
0011b
0010b
1001b
WREN - Set Write Enable Latch
The FM25H20 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
S
0
C
1
2
3
4
5
6
7
D
Q
0
0
0
0
Hi-Z
0
1
1
0
Figure 5. WREN Bus Configuration
Rev. 2.2
Sept. 2010
Page 5 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
