FM25H20 - 2Mb SPI FRAM
W
S
HOLD
C
Instruction Decode
Clock Generator
Control Logic
Write Protect
32768 x 64
FRAM Array
Instruction Register
Address Register
Counter
D
18
8
Data I/O Register
3
Nonvolatile Status
Register
Q
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/S
I/O
Input
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the C signal. A falling edge on /S must occur prior
to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 40 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.
Write Protect: This active low pin prevents write operations only to the Status
Register. A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of C and is ignored at other times. It should always be driven to a valid
logic level to meet I
DD
specifications.
* D may be connected to Q for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* Q may be connected to D for a single pin data interface.
Power Supply (2.7V to 3.6V)
Ground
C
Input
/HOLD
/W
D
Input
Input
Input
Q
Output
VDD
VSS
Supply
Supply
Rev. 2.2
Sept. 2010
Page 2 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
