FM25CL64
RDSR - Read Status Register
WRSR – Write Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25CL64 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Note that on the FM25CL64, /WP only prevents
writing to the Status register, not the memory array.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
features. They are nonvolatile! The WEL flag
Status Register & Write Protection
indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the
status register has no effect on its state. This bit is
internally set and cleared via the WREN and WRDI
commands, respectively.
The write protection features of the FM25CL64 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status register. As described above,
writes to the status register are performed using the
WRSR command and subject to the /WP pin. The
Status register is organized as follows.
BP1 and BP0 are memory block write protection
bits. They specify portions of memory that are write
protected as shown in the following table.
Table 2. Status Register
Table 3. Block Memory Write Protection
Bit
7
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
BP1
BP0
Protected Address Range
None
Name WPEN
WEL
0
0
1
1
0
1
0
1
1800h to 1FFFh (upper ¼)
1000h to 1FFFh (upper ½)
0000h to 1FFFh (all)
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The WPEN, BP1 and BP0 control write protection
Rev. 2.1
Apr. 2003
Page 6 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
