FM25040B - 4Kb 5V SPI F-RAM
CS
0
SCK
op-code
SI
SO
0
0
0
0
A
0
1
0
7
MSB
Hi-Z
6
Byte Address
5 4 3 2
Data
4 3
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
1
0
7
6
5
2
1
0
LSB
0
LSB MSB
Figure 9. Memory Write
CS
0
SCK
op-code
SI
SO
0
0
0
0
A
0
1
1
7
MSB
Hi-Z
Byte Address
6 5 4 3 2
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
1
0
LSB
7 6
MSB
5
Data Out
4 3 2
1
0
LSB
0
LSB
Figure 10. Memory Read
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each access: read or write. The F-RAM
architecture is based on an array of rows and
columns. Each access causes a cycle for an entire
row. In the FM25040B, a row is 64 bits wide. Every
8-byte boundary marks the beginning of a new row.
Endurance can be optimized by ensuring frequently
accessed data is located in different rows.
Regardless, F-RAM read and write endurance is
effectively unlimited at the 20MHz clock speed.
Even at 2000 accesses per second to the same row, 15
years time will elapse before 10
12
endurance cycles
occur.
Rev. 1.2
Feb. 2011
Page 8 of
13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
