FM24V02 - 256Kb I2C FRAM
AC Parameters (TA = -40° C to + 85° C, VDD =2.0V to 3.6V unless otherwise specified)
F/S-mode
HS-mode
(CL<500pF)
(CL<100pF)
Symbol Parameter
Min
Max
Min
Max
Units Notes
fSCL
tLOW
tHIGH
tAA
SCL Clock Frequency
0
500
260
1.0
0
160
60
3.4
MHz
ns
1
Clock Low Period
Clock High Period
SCL Low to SDA Data Out Valid
ns
450
130
ns
tBUF
Bus Free Before New Transmission
Start Condition Hold Time
Start Condition Setup for Repeated Start
Data In Hold
0.5
260
260
0
0.3
160
160
0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
Data In Setup
50
10
3
2
2
Input Rise Time
120
120
80
80
tF
Input Fall Time
tSU:STO
Stop Condition Setup
260
0
160
0
tDH
Data Output Hold (from SCL @ VIL)
Noise Suppression Time Constant on SCL, SDA
tSP
50
5
Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations.
1. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL
(max).
2. This parameter is periodically sampled and not 100% tested.
3. In HS-mode and VDD < 2.7V, the tSU:DAT (min.) spec is 15ns.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
Min
Max
Units Notes
CI/O
CIN
Input/Output Capacitance (SDA)
Input Capacitance
-
-
8
6
pF
pF
1
1
Notes
1. This parameter is periodically sampled and not 100% tested.
Power Cycle Timing (TA = -40° C to +85° C, VDD = 2.0V to 3.6V)
Symbol Parameter
Min
Max
Units Notes
tVR
tVF
VDD Rise Time
50
100
250
0
-
µ
s/V
1,2
1,2
VDD Fall Time
-
-
µs/V
µ
µ
µ
tPU
Power Up (VDD min) to First Access (Start condition)
Last Access (Stop condition) to Power Down (VDD min)
Recovery Time from Sleep Mode
s
s
s
tPD
tREC
Notes
-
-
400
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on VDD waveform.
Rev. 0.1
Mar. 2009
Page 12 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
