FM22LD16 - 256Kx16 FRAM
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(17:0)
Input
/CE
Input
/WE
Input
/OE
DQ(15:0)
/UB
/LB
VDD
VSS
Input
I/O
Input
Input
Supply
Supply
Pin Description
Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array.
The lowest two address lines A(1:0) may be used for page mode read and write
operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is
low. The entire address is latched internally on the falling edge of /CE. Subsequent
changes to the A(1:0) address inputs allow page mode operation when /CE is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM22LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of
/WE latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM22LD16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
Supply Voltage: 3.3V
Ground
Rev. 1.0
Oct. 2008
Page 2 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
