FM21LD16 - 128Kx16 FRAM
Address Latch & Write Protect
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(16:0)
Input
/CE
Input
/WE
Input
/OE
DQ(15:0)
/UB
Input
I/O
Input
/LB
Input
VDD
VSS
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is
low. The entire address is latched internally on the falling edge of /CE. Subsequent changes
to the A(1:0) address inputs allow page mode operation when /CE is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21LD16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. Deasserting /UB high
tri-states the DQ pins. If the user does not perform byte writes and the device is not
configured as a 256Kx8, the /UB and /LB pins may be tied to ground.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. Deasserting /LB high tri-
states the DQ pins. If the user does not perform byte writes and the device is not configured
as a 256Kx8, the /UB and /LB pins may be tied to ground.
Supply Voltage
Ground
Rev. 1.0
Dec. 2009
Block & Row Decoder
Page 2 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
