FM21L16 - 128Kx16 FRAM
Power Cycle and Sleep Mode Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
tZZH
tWEZZ
tZZL
Parameter
Min
450
0
50
100
-
Max
-
-
-
-
20
-
-
Units
µs
µs
µs/V
µs/V
ns
Notes
Power Up to First Access Time (after VTP is reached)
Last Write (/WE high) to Power Down Time (prior to VTP)
VDD Rise Time
VDD Fall Time
/ZZ Active to DQ Hi-Z Time
1,2
1,2
Last Write to Sleep Mode Entry Time
/ZZ Active Low Time
0
1
µs
µs
tZZEN
tZZEX
Notes
1. Slope measured at any point on VDD waveform.
Sleep Mode Entry Time (/ZZ low to /CE don’t care)
-
-
0
450
µs
µs
Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)
2. Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times 3 ns
0 to 3V
Input and Output Timing Levels
Output Load Capacitance
1.5V
30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 1.0
Sept. 2007
Page 10 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
