Electrical Characteristics
TA = 0 - 70°C (Com m ercial)
Symbol
Parameters
Max
Min
Test Conditions
All Voltages Referenced to V
V
Supply Voltage
4.75V
5.25V
CC
SS
V
Input High Voltage
Input Low Voltage
Output High Level
Output Low Level
Input Leakage Current
Output Leakage Current
2.4V
-1.0V
2.4V
V +1
IH
CC
V
0.8V
IL
VOH
VOL
IOUT = - 5mA
IOUT = 4.2mA
0.4V
90µA
90µA
V
-90µA
-90µA
0V ≤ V ≤ 6.5V, All Other Pins Not Under Test = 0V
i(L)
IN
V
0V ≤ V , 0V ≤ VOUT ≤ 5.5V
0(L)
IN
DM512K72DT6
33MHz Typ(1)
1166mA
-15 Max
Symbol
Operating Current
-12 Max
Test Condition
Notes
ICC1
Random Read
2465mA 1970mA /RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
1745mA 1385mA /CAL, /G and Addresses Cycling: tPC = tPC Minimum
1430mA 1160mA /G and Addresses Cycling: tAC = tAC Minimum
2, 3
ICC2
ICC3
ICC4
ICC5
ICC6
ICCT
Fast Page Mode Read
Static Column Read
Random Write
761mA
2, 4
2, 4
2, 3
2, 4
671mA
1391mA
626mA
11mA
2150mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
1700mA
Fast Page Mode Write
Standby
1655mA 1295mA /CAL, /WE and Addresses Cycling: tPC = tPC Minimum
11mA
—
11mA
—
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
1
Average Typical
446mA
See "Estimating EDRAM Operating Power" Application Note
Operating Current
DM512K64DT6
33MHz Typ(1)
1056mA
-15 Max
Symbol
Operating Current
-12 Max
Test Condition
Notes
ICC1
Random Read
2240mA 1790mA /RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
1600mA 1270mA /CAL, /G and Addresses Cycling: tPC = tPC Minimum
1320mA 1070mA /G and Addresses Cycling: tAC = tAC Minimum
2, 3
ICC2
ICC3
ICC4
ICC5
ICC6
ICCT
Fast Page Mode Read
Static Column Read
Random Write
696mA
2, 4
2, 4
2, 3
2, 4
616mA
1256mA
576mA
10mA
1960mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
1550mA
Fast Page Mode Write
Standby
1520mA 1190mA /CAL, /WE and Addresses Cycling: tPC = tPC Minimum
10mA
—
10mA
—
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
1
Average Typical
416mA
See "Estimating EDRAM Operating Power" Application Note
Operating Current
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = V
IL
(4) ICC is measured with a maximum of one address change while /CAL = V
IH
2-148
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
